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www.latticesemi.com 1 ds1014_01.5 isppac-powr1014/a in-system programmable power supply supervisor, reset generator and sequencing controller august 2007 data sheet ds1014 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information h erein are subject to change without notice. features monitor and control multiple power supplies simultaneously monitors up to 10 power supplies provides up to 14 output control signals programmable digital and analog circuitry embedded pld for sequence control 24-macrocell cpld implements both state machines and combinatorial logic functions embedded programmable timers four independent timers 32? to 2 second intervals for timing sequences analog input monitoring 10 independent analog monitor inputs two programmable threshold comparators per analog input hardware window comparison 10-bit adc for i 2 c monitoring (isppac- powr1014a only) high-voltage fet drivers power supply ramp up/down control programmable current and voltage output independently con?urable for fet control or digital output 2-wire (i 2 c/smbus compatible) interface comparator status monitor adc readout direct control of inputs and outputs power sequence control only available with isppac-powr1014a 3.3v operation, wide supply range 2.8v to 3.96v in-system programmable through jtag industrial temperature range: -40? to +85? 48-pin tqfp package, lead-free option application block diagram description lattices power manager ii isppac-powr1014/a is a general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile e 2 cmos technology. the isppac-powr1014/a device provides 10 independent analog input channels to monitor up to 10 power supply test points. each of these input channels has two inde- pendently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-com- pare) monitor functions. four general-purpose digital inputs are also provided for miscellaneous control func- tions. the isppac-powr1014/a provides 14 open-drain digi- tal outputs that can be used for controlling dc-dc con- verters, low-drop-out regulators (ldos) and opto- couplers, as well as for supervisory and general-pur- pose logic interface functions. two of these outputs (hvout1-hvout2) may be con?ured as high-voltage pol#1 pol#n cpu isppac-powr1014a signals 4 timers adc* *isppac-po w r1014a only. 4 digital inp u ts i 2 c interface i 2 c b u s* 10 analog inp u ts and v oltage monitors di g ital monitorin g other board circ u itry v oltage monitoring ena b les primary s u pply primary s u pply primary s u pply primary s u pply primary s u pply 12 digital o u tp u ts other control/s u per v isory cpld 24 macrocells 53 inp u ts 2 mosfet dri v ers 3.3 v 2.5 v 1. 8v
lattice semiconductor isppac-powr1014/a data sheet 2 mosfet drivers. in high-voltage mode these outputs can provide up to 10v for driving the gates of n-channel mosfets so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. the isppac-powr1014/a incorporates a 24-macrocell cpld that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. the status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the cpld array, and all digital outputs may be controlled by the cpld. four independently programmable timers can create delays and time-outs ranging from 32? to 2 seconds. the cpld is programmed using logi- builder, an easy-to-learn language integrated into the pac-designer software. control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. the on-chip 10-bit a/d converter is used to monitor the v mo n voltage through the i 2 c bus of the isppac- powr1014a device. the i 2 c bus/smbus interface allows an external microcontroller to measure the voltages connected to the v mo n inputs, read back the status of each of the v mo n comparator and pld outputs, control logic signals i n 2 to i n 4 and control the output pins (isppac-powr1014a only). figure 1. isppac-powr1014/a block diagram cpld 24 macrocells 53 inputs jtag logic clock oscillator timers (4) i 2 c interface adc* measurement control logic* *isppac-po w r1014a only. l a t i g i d 4 s t u p n i s t u p n i g o l a n a 0 1 s r o t i n o m e g a t l o v d n a t e f 2 s r e v i r d n i a r d - n e p o 2 1 s t u p t u o l a t i g i d g n i t u o r t u p t u o l o o p v mon1 v mon2 v mon3 v mon4 v mon5 v mon6 v mon7 v mon 8 v mon9 v mon10 in1 in2 in3 in4 out3/(smba*) out4 out5 out6 out7 out 8 out9 out10 out11 out12 out13 out14 h v out1 h v out2 j c c v o d t s m t k c t tdisel k l c d l p i d t i d t a k l c m sda (po w r1014a o n scl (po w r1014a o n b t e s e r g o r p c c v gndd (2) gnda v cca v ccd (2) v ccinp
lattice semiconductor isppac-powr1014/a data sheet 3 pin descriptions number name pin type voltage range description 44 i n 1 digital input vcci n p 1 pld logic input 1 registered by mclk 46 i n 2 digital input vcci n p 1 pld logic input 2 registered by mclk 47 i n 3 digital input vcci n p 1 pld logic input 3 registered by mclk 48 i n 4 digital input vcci n p 1 pld logic input 4 registered by mclk 25 vmo n 1 analog input -0.3v to 5.87v 4 voltage monitor 1 input 26 vmo n 2 analog input -0.3v to 5.87v 4 voltage monitor 2 input 27 vmo n 3 analog input -0.3v to 5.87v 4 voltage monitor 3 input 28 vmo n 4 analog input -0.3v to 5.87v 4 voltage monitor 4 input 32 vmo n 5 analog input -0.3v to 5.87v 4 voltage monitor 5 input 33 vmo n 6 analog input -0.3v to 5.87v 4 voltage monitor 6 input 34 vmo n 7 analog input -0.3v to 5.87v 4 voltage monitor 7 input 35 vmo n 8 analog input -0.3v to 5.87v 4 voltage monitor 8 input 36 vmo n 9 analog input -0.3v to 5.87v 4 voltage monitor 9 input 37 vmo n 10 analog input -0.3v to 5.87v 4 voltage monitor 10 input 7, 31 g n dd 5 ground ground digital ground 30 g n da 5 ground ground analog ground 41, 23 vccd 6 power 2.8v to 3.96v core vcc, main power supply 29 vcca 6 power 2.8v to 3.96v analog power supply 45 vcci n p power 2.25v to 5.5v vcc for i n [1:4] inputs 20 vccj power 2.25v to 3.6v vcc for jtag logic interface pins 24 vccprog power 3.0v to 3.6v vcc for e 2 programming when the device is n ot powered by v ccd and v cca 15 hvout1 open drain output 7 0v to 10v open-drain output 1 current source/sink 12.5? to 100? source 100? to 3000? sink high-voltage fet gate driver 1 14 hvout2 open drain output 7 0v to 10v open-drain output 2 current source/sink 12.5? to 100? source 100? to 3000? sink high-voltage fet gate driver 2 13 smba_out3 open drain output 7 0v to 5.5v open-drain output 3, (smbus alert active low, isppac-powr1014a only). 12 out4 open drain output 7 0v to 5.5v open-drain output 4 11 out5 open drain output 7 0v to 5.5v open-drain output 5 10 out6 open drain output 7 0v to 5.5v open-drain output 6 9 out7 open drain output 7 0v to 5.5v open-drain output 7 8 out8 open drain output 7 0v to 5.5v open-drain output 8 6 out9 open drain output 7 0v to 5.5v open-drain output 9 5 out10 open drain output 7 0v to 5.5v open-drain output 10 4 out11 open drain output 7 0v to 5.5v open-drain output 11 3 out12 open drain output 7 0v to 5.5v open-drain output 12 2 out13 open drain output 7 0v to 5.5v open-drain output 13 1 out14 open drain output 7 0v to 5.5v open-drain output 14 40 resetb 8 digital i/o 0v to 3.96v device reset (active low) - internal pull-up 42 pldclk digital output 0v to 3.96v 250khz pld clock output (tristate), cmos output - internal pull-up
lattice semiconductor isppac-powr1014/a data sheet 4 43 mclk digital i/o 0v to 3.96v 8mhz clock i/o (tristate), cmos drive - internal pull-up 21 tdo digital output 0v to 5.5v jtag test data out 22 tck digital input 0v to 5.5v jtag test clock input 16 tms digital input 0v to 5.5v jtag test mode select - internal pull-up 18 tdi digital input 0v to 5.5v jtag test data in, tdisel pin = 1 - internal pull-up 17 atdi digital input 0v to 5.5v jtag test data in (alternate), tdisel pin = 0 - internal pull-up 19 tdisel digital input 0v to 5.5v select tdi/atdi input - internal pull-up 39 scl 9 digital input 0v to 5.5v i 2 c serial clock input (isppac-powr1014a only) 38 sda 9 digital i/o 0v to 5.5v i 2 c serial data, bi-directional pin, open drain (isppac-powr1014a only) 1. [i n 1...i n 4] are inputs to the pld. the thresholds for these pins are referenced by the voltage on vcci n p. unused i n x inputs should be tied to g n dd. 2. i n 1 pin can also be controlled through jtag interface. 3. [i n 2..i n 4] can also be controlled through i 2 c/smbus interface (isppac-powr1014a only). 4. the vmo n inputs can be biased independently from vcca. unused vmo n inputs should be tied to g n dd. 5. g n da and g n dd pins must be connected together on the circuit board. 6. vccd and vcca pins must be connected together on the circuit board. 7. open-drain outputs require an external pull-up resistor to a supply. 8. the resetb pin should only be used for cascading two or more isppac-powr1014/a devices. 9. these pins should be connected to g n dd (isppac-powr1014 device only). pin descriptions (cont.) number name pin type voltage range description
lattice semiconductor isppac-powr1014/a data sheet 5 absolute maximum ratings absolute maximum ratings are shown in the table below. stresses beyond those listed may cause permanent dam- age to the device. functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this speci?ation is not implied. recommended operating conditions analog speci?ations symbol parameter conditions min. max. units v ccd core supply -0.5 4.5 v v cca analog supply -0.5 4.5 v v cci n p digital input supply (i n [1:4]) -0.5 6 v v ccj jtag logic supply -0.5 6 v v ccprog e 2 programming supply -0.5 4 v v i n digital input voltage (all digital i/o pins) -0.5 6 v v mo n v mo n input voltage -0.5 6 v v tri voltage applied to tri-stated pins hvout[1:2] -0.5 11 v out[3:14] -0.5 6 v i si n kmaxtotal maximum sink current on any output 23 ma t s storage temperature -65 150 o c t a ambient temperature -65 125 o c symbol parameter conditions min. max. units v ccd, v cca core supply voltage at pin 2.8 3.96 v v cci n p digital input supply for i n [1:4] at pin 2.25 5.5 v v ccj jtag logic supply voltage at pin 2.25 3.6 v v ccprog e 2 programming supply at pin during e 2 programming 3.0 3.6 v v i n input voltage at digital input pins -0.3 5.5 v v mo n input voltage at v mo n pins -0.3 5.9 v v out open-drain output voltage out[3:14] pins -0.3 5.5 v hvout[1:2] pins in open- drain mode -0.3 10.4 v t aprog ambient temperature during programming -40 85 o c t a ambient temperature power applied -40 85 o c symbol parameter conditions min. typ. max. units i cc 1 supply current 20 ma i cci n p supply current 5ma i ccj supply current 1ma i ccprog supply current during programming cycle 20 ma 1. includes currents on v ccd and v cca supplies.
lattice semiconductor isppac-powr1014/a data sheet 6 voltage monitors high voltage fet drivers symbol parameter conditions min. typ. max. units r i n input resistance 55 65 75 k c i n input capacitance 8 pf v mo n range programmable trip-point range 0.075 5.867 v v z sense n ear-ground sense threshold 70 75 80 mv v mo n accuracy absolute accuracy of any trip-point 1 0.3 0.9 % hyst hysteresis of any trip-point (relative to setting) 1% 1. guaranteed by characterization across v cca range, operating temperature, process. symbol parameter conditions min. typ. max. units v pp gate driver output voltage 10v setting 9.6 10 10.4 v 8v setting 7.7 8 8.3 6v setting 5.8 6 6.2 i outsrc gate driver source current (high state) four settings in software 12.5 ? 25 50 100 i outsi n k gate driver sink current (low state) fast off mode 2000 3000 ? controlled ramp settings 100 250 500
lattice semiconductor isppac-powr1014/a data sheet 7 adc characteristics 1 adc error budget across entire operating temperature range 1 power-on reset symbol parameter conditions min. typ. max. units adc resolution 10 bits t co n vert conversion time time from i 2 c request 100 ? v i n input range full scale programmable attenuator = 1 0 2.048 v programmable attenuator = 3 0 5.9 2 v adc step size lsb programmable attenuator = 1 2 mv programmable attenuator = 3 6 mv eattenuator error due to attenuator programmable attenuator = 3 +/- 0.1 % 1. isppac-powr1014a only. 2. maximum voltage is limited by v mo n x pin (theoretical maximum is 6.144v). symbol parameter conditions min. typ. max. units tadc error total measurement error at any voltage 2 measurement range 600 mv - 2.048v, attenuator =1 -8 +/-4 8 mv 1. isppac-powr1014a only. 2. total error, guaranteed by characterization, includes i n l, d n l, gain, offset, and psr specs of the adc. symbol parameter conditions min. typ. max. units t good power-on reset to valid vmo n comparator output 500 ? v tl threshold below which resetb is low 1 2.3 v v th threshold above which resetb is high 1 2.7 v v t threshold above which resetb is valid 1 0.8 v t por minimum duration dropout required to trigger resetb 15s c l capacitive load on resetb for master/slave operation 200 pf 1. corresponds to vcca and vccd supply voltages.
lattice semiconductor isppac-powr1014/a data sheet 8 ac/transient characteristics over recommended operating conditions symbol parameter conditions min. typ. max. units voltage monitors t pd16 propagation delay input to output glitch ?ter off 16 ? t pd64 propagation delay input to output glitch ?ter o n 64 ? oscillators f clk internal master clock frequency (mclk) 7.6 8 8.4 mhz f clkext externally applied master clock (mclk) 7.2 8.8 mhz f pldclk pldclk output frequency f clk = 8mhz 250 khz timers timeout range range of programmable timers (128 steps) f clk = 8mhz 0.032 1966 ms resolution spacing between available adjacent timer intervals 13 % accuracy timer accuracy f clk = 8mhz -6.67 -12.5 %
lattice semiconductor isppac-powr1014/a data sheet 9 digital speci?ations over recommended operating conditions symbol parameter conditions min. typ. max. units i il ,i ih input leakage, no pull-up/pull-down +/-10 ? i oh-hvout output leakage current hvout[1:2] in open drain mode and pulled up to 10v 35 60 ? i pu input pull-up current (tms, tdi, tdisel, atdi, mclk, pldclk, resetb) 70 ? v il voltage input, logic low 1 tdi, tms, atdi, tdisel, 3.3v supply 0.8 v tdi, tms, atdi, tdisel, 2.5v supply 0.7 scl, sda 30% v ccd i n [1:4] 30% v cci n p v ih voltage input, logic high 1 tdi, tms, atdi, tdisel, 3.3v supply 2.0 v tdi, tms, atdi, tdisel, 2.5v supply 1.7 scl, sda 70% v ccd v ccd i n [1:4] 70% v cci n p v cci n p v ol hvout[1:2] (open drain mode), i si n k = 10ma 0.8 v out[3:14] i si n k = 20ma 0.8 tdo,mclk,pldclk i si n k = 4ma 0.4 v oh tdo, mclk, pldclk i src = 4ma v ccd - 0.4 v i si n ktotal 2 all digital outputs 67 ma 1. i n [1:4] referenced to v cci n p ; tdo, tdi, tms, atdi, tdisel referenced to v ccj ; scl, sda referenced to v ccd. 2. sum of maximum current sink from all digital outputs combined. reliable operation is not guaranteed if this value is exceeded .
lattice semiconductor isppac-powr1014/a data sheet 10 i 2 c port characteristics 1 symbol de?ition 100khz 400khz units min. max. min. max. f i 2 c i 2 c clock/data rate 100 2 400 2 khz t su;sta after start 4.7 0.6 us t hd;sta after start 4 0.6 us t su;dat data setup 250 100 ns t su;sto stop setup 4 0.6 us t hd;dat data hold; scl= vih_min = 2.1v 0.3 3.45 0.3 0.9 us t low clock low period 4.7 10 1.3 10 us t high clock high period 4 0.6 us t f fall time; 2.25v to 0.65v 300 300 ns t r rise time; 0.65v to 2.25v 1000 300 ns t timeout detect clock low timeout 25 35 25 35 ms t por device must be operational after power-on reset 500 500 ms t buf bus free time between stop and start condition 4.7 1.3 us 1. applies to isppac-powr1014a only. 2. if f i 2 c is less than 50khz, then the adc do n e status bit is not guaranteed to be set after a valid conversion request is completed. in this case, waiting for the t co n vert minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for readout. when f i2c is greater than 50khz, adc conversion complete is ensured by waiting for the do n e status bit.
lattice semiconductor isppac-powr1014/a data sheet 11 timing for jtag operations figure 2. erase (user erase or erase all) timing diagram figure 3. programming timing diagram symbol parameter conditions min. typ. max. units t ispe n program enable delay time 10 ? t ispdis program disable delay time 30 ? t hvdis high voltage discharge time, program 30 s t hvdis high voltage discharge time, erase 200 ? t ce n falling edge of tck to tdo active 10 ns t cdis falling edge of tck to tdo disable 10 ns t su1 setup time 5 ns t h hold time 10 ns t ckh tck clock pulse width, high 20 ns t ckl tck clock pulse width, low 20 ns f max maximum tck clock frequency 25 mhz t co falling edge of tck to valid output 10 ns t pwv verify pulse width 30 ? t pwp programming pulse width 20 ms vih vil vih vil update-ir run-test/idle (erase) select-dr scan clock to shift-ir state and shift in the discharge instruction, then clock to the run-test/idle state run-test/idle (discharge) specified by the data sheet tms tck state t h t h t h t h t h t h t su1 t su1 t su1 t su1 t su1 t su1 t su2 t ckh t ckh t ckh t ckh t ckh t gkl t gkl tms tck state vih vil vih vi l update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction, which will stop the discharge process update-ir t su1 t su1 t su1 t su1 t su1 t h t h t h t h t h t ckl t pwp t ckh t ckh t ckh t ckh t ckl
lattice semiconductor isppac-powr1014/a data sheet 12 figure 4. verify timing diagram figure 5. discharge timing diagram theory of operation analog monitor inputs the isppac-powr1014/a provides 10 independently programmable voltage monitor input circuits as shown in figure 6. two individually programmable trip-point comparators are connected to an analog monitoring input. each comparator reference has 372 programmable trip points over the range of 0.672v to 5.867v. additionally, a 75mv ?ero-detect threshold is selectable which allows the voltage monitors to determine if a monitored signal has dropped to ground level. this feature is especially useful for determining if a power supplys output has decayed to a substantially inactive condition after it has been switched off. tms tck state vih vil vih vil update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction update-ir t h t h t h t h t h t ckh t ckh t ckh t ckl t pwv t ckh t ckl t su1 t su1 t su1 t su1 t su1 tms tck state vih vil vih vil update-ir run-test/idle (erase or program) select-dr scan clock to shift-ir state and shift in the verify instruction, then clock to the run-test/idle state run-test/idle (verify) specified by the data sheet actual t h t h t h t h t h t h t su1 t ckh t hvdis (actual) t ckh t ckh t ckh t ckl t pwp t pwv t ckh t ckl t pwv t su1 t su1 t su1 t su1 t su1
lattice semiconductor isppac-powr1014/a data sheet 13 figure 6. isppac-powr1014/a voltage monitors figure 6 shows the functional block diagram of one of the 10 voltage monitor inputs - ? (where x = 1...10). each voltage monitor can be divided into three sections: analog input, window control, and filtering. the voltage input is monitored by two individually programmable trip-point comparators, shown as compa and compb. table 1 shows all trip points and the range to which any comparators threshold can be set. each comparator outputs a high signal to the pld array if the voltage at its positive terminal is greater than its pro- grammed trip point setting, otherwise it outputs a low signal. a hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a result of input noise. the hysteresis provided by the voltage monitor is a function of the input divider setting. table 3 lists the typical hysteresis versus voltage monitor trip-point. agood logic signal all the vmo n comparators auto-calibrate immediately after a power-on reset event. during this time, the digital glitch ?ters are also initialized. this process completion is signalled by an internally generated logic signal: agood. all logic using the vmo n comparator logic signals must wait for the agood signal to become active. programmable over-voltage and under-voltage thresholds figure 7 (a) shows the power supply ramp-up and ramp-down voltage waveforms. because of hysteresis, the com- parator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply. glitch filter mux trip point a + + comp a comp b comp a/ w indo w select v monxb logic signal v monx trip point b analog inp u t w indo w control filtering isppac-po w r1014/a to adc (po w r1014a only) v monxa logic signal pld array v monx stat u s i 2 c interface unit (po w r1014a only) glitch filter
lattice semiconductor isppac-powr1014/a data sheet 14 figure 7. (a) power supply voltage ramp-up and ramp-down waveform and the resulting comparator output, (b) corresponding to upper and lower trip points during power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage crosses the upper trip point (utp). during ramp down the comparator output changes from logic state 1 to 0 when the power supply voltage crosses the lower trip point (ltp). to monitor for over voltage fault conditions, the utp should be used. to monitor under-voltage fault conditions, the ltp should be used. tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. utp ltp monitored po w er s u pply v otlage comparator logic o u tp u t (a) ( b )
lattice semiconductor isppac-powr1014/a data sheet 15 table 1. trip point table used for over-voltage detection coarse range setting fine range setting 123456789101112 1 0.806 0.960 1.143 1.360 1.612 1.923 2.290 2.719 3.223 3.839 4.926 5.867 2 0.802 0.955 1.137 1.353 1.603 1.913 2.278 2.705 3.206 3.819 4.900 5.836 3 0.797 0.950 1.131 1.346 1.595 1.903 2.266 2.691 3.190 3.799 4.875 5.806 4 0.793 0.945 1.125 1.338 1.586 1.893 2.254 2.677 3.173 3.779 4.849 5.775 5 0.789 0.940 1.119 1.331 1.578 1.883 2.242 2.663 3.156 3.759 4.823 5.745 6 0.785 0.935 1.113 1.324 1.570 1.873 2.230 2.649 3.139 3.739 4.798 5.714 7 0.781 0.930 1.107 1.317 1.561 1.863 2.219 2.634 3.122 3.719 4.772 5.683 8 0.776 0.925 1.101 1.310 1.553 1.853 2.207 2.620 3.106 3.699 4.746 5.653 9 0.772 0.920 1.095 1.303 1.544 1.843 2.195 2.606 3.089 3.679 4.721 5.622 10 0.768 0.915 1.089 1.296 1.536 1.833 2.183 2.592 3.072 3.659 4.695 5.592 11 0.764 0.910 1.083 1.289 1.528 1.823 2.171 2.578 3.055 3.639 4.669 5.561 12 0.760 0.905 1.077 1.282 1.519 1.813 2.159 2.564 3.038 3.619 4.644 5.531 13 0.755 0.900 1.071 1.275 1.511 1.803 2.147 2.550 3.022 3.599 4.618 5.500 14 0.751 0.895 1.065 1.268 1.502 1.793 2.135 2.535 3.005 3.579 4.592 5.470 15 0.747 0.890 1.059 1.261 1.494 1.783 2.123 2.521 2.988 3.559 4.567 5.439 16 0.743 0.885 1.053 1.254 1.486 1.773 2.111 2.507 2.971 3.539 4.541 5.408 17 0.739 0.880 1.047 1.246 1.477 1.763 2.099 2.493 2.954 3.519 4.515 5.378 18 0.734 0.875 1.041 1.239 1.469 1.753 2.087 2.479 2.938 3.499 4.490 5.347 19 0.730 0.870 1.035 1.232 1.460 1.743 2.075 2.465 2.921 3.479 4.464 5.317 20 0.726 0.865 1.029 1.225 1.452 1.733 2.063 2.450 2.904 3.459 4.438 5.286 21 0.722 0.860 1.024 1.218 1.444 1.723 2.052 2.436 2.887 3.439 4.413 5.256 22 0.718 0.855 1.018 1.211 1.435 1.713 2.040 2.422 2.871 3.419 4.387 5.225 23 0.713 0.850 1.012 1.204 1.427 1.703 2.028 2.408 2.854 3.399 4.361 5.195 24 0.709 0.845 1.006 1.197 1.418 1.693 2.016 2.394 2.837 3.379 4.336 5.164 25 0.705 0.840 1.000 1.190 1.410 1.683 2.004 2.380 2.820 3.359 4.310 5.133 26 0.701 0.835 0.994 1.183 1.402 1.673 1.992 2.365 2.803 3.339 4.284 5.103 27 0.697 0.830 0.988 1.176 1.393 1.663 1.980 2.351 2.787 3.319 4.259 5.072 28 0.692 0.825 0.982 1.169 1.385 1.653 1.968 2.337 2.770 3.299 4.233 5.042 29 0.688 0.820 0.976 1.161 1.377 1.643 1.956 2.323 2.753 3.279 4.207 5.011 30 0.684 0.815 0.970 1.154 1.368 1.633 1.944 2.309 2.736 3.259 4.182 4.981 31 0.680 0.810 0.964 1.147 1.623 1.932 2.295 3.239 4.156 4.950 low-v sense 75mv
lattice semiconductor isppac-powr1014/a data sheet 16 table 2. trip point table used for under-voltage detection fine range setting 123456789101112 1 0.797 0.950 1.131 1.346 1.595 1.903 2.266 2.691 3.190 3.799 4.875 5.806 2 0.793 0.945 1.125 1.338 1.586 1.893 2.254 2.677 3.173 3.779 4.849 5.775 3 0.789 0.940 1.119 1.331 1.578 1.883 2.242 2.663 3.156 3.759 4.823 5.745 4 0.785 0.935 1.113 1.324 1.570 1.873 2.230 2.649 3.139 3.739 4.798 5.714 5 0.781 0.930 1.107 1.317 1.561 1.863 2.219 2.634 3.122 3.719 4.772 5.683 6 0.776 0.925 1.101 1.310 1.553 1.853 2.207 2.620 3.106 3.699 4.746 5.653 7 0.772 0.920 1.095 1.303 1.544 1.843 2.195 2.606 3.089 3.679 4.721 5.622 8 0.768 0.915 1.089 1.296 1.536 1.833 2.183 2.592 3.072 3.659 4.695 5.592 9 0.764 0.910 1.083 1.289 1.528 1.823 2.171 2.578 3.055 3.639 4.669 5.561 10 0.760 0.905 1.077 1.282 1.519 1.813 2.159 2.564 3.038 3.619 4.644 5.531 11 0.755 0.900 1.071 1.275 1.511 1.803 2.147 2.550 3.022 3.599 4.618 5.500 12 0.751 0.895 1.065 1.268 1.502 1.793 2.135 2.535 3.005 3.579 4.592 5.470 13 0.747 0.890 1.059 1.261 1.494 1.783 2.123 2.521 2.988 3.559 4.567 5.439 14 0.743 0.885 1.053 1.254 1.486 1.773 2.111 2.507 2.971 3.539 4.541 5.408 15 0.739 0.880 1.047 1.246 1.477 1.763 2.099 2.493 2.954 3.519 4.515 5.378 16 0.734 0.875 1.041 1.239 1.469 1.753 2.087 2.479 2.938 3.499 4.490 5.347 17 0.730 0.870 1.035 1.232 1.460 1.743 2.075 2.465 2.921 3.479 4.464 5.317 18 0.726 0.865 1.029 1.225 1.452 1.733 2.063 2.450 2.904 3.459 4.438 5.286 19 0.722 0.860 1.024 1.218 1.444 1.723 2.052 2.436 2.887 3.439 4.413 5.256 20 0.718 0.855 1.018 1.211 1.435 1.713 2.040 2.422 2.871 3.419 4.387 5.225 21 0.713 0.850 1.012 1.204 1.427 1.703 2.028 2.408 2.854 3.399 4.361 5.195 22 0.709 0.845 1.006 1.197 1.418 1.693 2.016 2.394 2.837 3.379 4.336 5.164 23 0.705 0.840 1.000 1.190 1.410 1.683 2.004 2.380 2.820 3.359 4.310 5.133 24 0.701 0.835 0.994 1.183 1.402 1.673 1.992 2.365 2.803 3.339 4.284 5.103 25 0.697 0.830 0.988 1.176 1.393 1.663 1.980 2.351 2.787 3.319 4.259 5.072 26 0.692 0.825 0.982 1.169 1.385 1.653 1.968 2.337 2.770 3.299 4.233 5.042 27 0.688 0.820 0.976 1.161 1.377 1.643 1.956 2.323 2.753 3.279 4.207 5.011 28 0.684 0.815 0.970 1.154 1.368 1.633 1.944 2.309 2.736 3.259 4.182 4.981 29 0.680 0.810 0.964 1.147 1.360 1.623 1.932 2.295 2.719 3.239 4.156 4.950 30 0.676 0.805 0.958 1.140 1.352 1.613 1.920 2.281 2.702 3.219 4.130 4.919 31 0.672 0.800 0.952 1.133 - 1.603 1.908 2.267 - 3.199 4.105 4.889 low-v sense 75mv
lattice semiconductor isppac-powr1014/a data sheet 17 table 3. comparator hysteresis vs. trip-point the window control section of the voltage monitor circuit is an a n d gate (with inputs: an inverted compa ? n ded with compb signal) and a multiplexer that supports the ability to develop a ?indow function without using any of the plds resources. through the use of the multiplexer, voltage monitors ? output may be set to report either the status of the ? comparator, or the window function of both comparator outputs. the voltage monitors ? output indicates whether the input signal is between or outside the two comparator thresholds. important: this windowing function is only valid in cases where the threshold of the ? comparator is set to a value higher than that of the ? comparator. table 4 shows the operation of window function logic. table 4. voltage monitor windowing logic n ote that when the ? output of the voltage monitor circuit is set to windowing mode, the ? output continues to monitor the output of the ? comparator. this can be useful in that the ? output can be used to augment the win- dowing function by determining if the input is above or below the windowing range. the third section in the isppac-powr1014/as input voltage monitor is a digital ?ter. when enabled, the compara- tor output will be delayed by a ?ter time constant of 64 ?, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. when the ?ter is disabled, the comparator output will be delayed by 16?. in both cases, enabled or disabled, the ?ters also provide synchroniza- tion of the input signals to the pld clock. this synchronous sampling feature effectively eliminates the possibility of race conditions from occurring in any subsequent logic that is implemented in the isppac-powr1014/as internal pld logic. the comparator status can be read from the i 2 c interface (isppac-powr1014a only). for details on the i 2 c inter- face, please refer to the i 2 c/smbus interface section of this data sheet. trip-point range (v) hysteresis (mv) low limit high limit 0.672 0.806 8 0.800 0.960 10 0.952 1.143 12 1.133 1.360 14 1.346 1.612 17 1.603 1.923 20 1.908 2.290 24 2.267 2.719 28 2.691 3.223 34 3.199 3.839 40 4.105 4.926 51 4.889 5.867 61 75 mv 0 (disabled) input voltage comp a comp b window (b and not a) comment v i n < trip-point b < trip-point a 0 0 0 outside window, low trip-point b < v i n < trip-point a 0 1 1 inside window trip-point b < trip-point a < v i n 1 1 0 outside window, high
lattice semiconductor isppac-powr1014/a data sheet 18 vmon voltage measurement with the on-chip analog to digital converter (adc, isppac- powr1014a only) the isppac-powr1014a has an on-chip analog to digital converter that can be used for measuring the voltages at the vmo n inputs. figure 8. adc monitoring vmon1 to vmon10 figure 8 shows the adc circuit arrangement within the isppac-powr1014a device. the adc can measure all analog input voltages through the multiplexer, adc mux. the programmable attenuator between the adc mux and the adc can be con?ured as divided-by-3 or divided-by-1 (no attenuation). the divided-by-3 setting is used to measure voltages from 0v to 6v range and divided-by-1 setting is used to measure the voltages from 0v to 2v range. a microcontroller can place a request for any vmo n voltage measurement at any time through the i 2 c bus (isp- pac-powr1014a only). upon the receipt of an i 2 c command, the adc will be connected to the i 2 c selected vmo n through the adc mux. the adc output is then latched into the i 2 c readout registers. calculation the algorithm to convert the adc code to the corresponding voltage takes into consideration the attenuation bit value. in other words, if the attenuation bit is set, then the 10-bit adc result is automatically multiplied by 3 to cal- culate the actual voltage at that vmo n input. thus, the i 2 c readout register is 12 bits instead of 10 bits. the follow- ing formula can always be used to calculate the actual voltage from the adc code. voltage at the vmonx pins vmo n = i 2 c readout register (12 bits 1 , converted to decimal) * 2mv 1 n ote: adc_value_high (8 bits), adc_value_low (4 bits) read from i 2 c/smbus interface (isppac-powr1014a only). v mon1 v mon2 v mon3 v mon10 v dda v ccinp adc mux adc programma b le analog atten u ator programma b le digital m u ltiplier internal v ref- 2.04 8v 4 10 x3 / x1 3 / 1 12 to i 2 c reado u t register (isppac-po w r1014a only) 5 from i 2 c adc mux register (isppac-po w r1014a only) 1
lattice semiconductor isppac-powr1014/a data sheet 19 pld block figure 9 shows the isppac-powr1014/a pld architecture, which is derived from the lattice's ispmach 4000 cpld. the pld architecture allows the ?xibility in designing various state machines and control functions used for power supply management. the a n d array has 53 inputs and generates 123 product terms. these 123 product terms are divided into three groups of 41 for each of the generic logic blocks, glb1, glb2, and glb3. each glb is made up of eight macrocells. in total, there are 24 macrocells in the isppac-powr1014/a device. the output signals of the isppac-powr1014/a device are derived from glbs as shown in figure 9. glb3 generates timer control. figure 9. isppac-powr1014/a pld architecture macrocell architecture the macrocell shown in figure 10 is the heart of the pld. the basic macrocell has ?e product terms that feed the or gate and the ?p-?p. the ?p-?p in each macrocell is independently con?ured. it can be programmed to function as a d-type or t-type ?p-?p. combinatorial functions are realized by bypassing the ?p-?p. the polarity control and xor gates provide additional ?xibility for logic synthesis. the ?p-?ps clock is driven from the com- mon pld clock that is generated by dividing the 8 mhz master clock by 32. the macrocell also supports asynchro- nous reset and preset functions, derived from either product terms, the global reset input, or the power-on reset signal. the resources within the macrocells share routing and contain a product term allocation array. the product term allocation array greatly expands the plds ability to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. and array 53 inp u ts 123 pt glo b al reset (reset b pin) o u tp u t feed b ack 24 v mon[1-10] 20 in[1:4] timer1 timer0 timer2 timer3 timer clock irp 1 8 pld clock 4 4 agood glb1 generic logic block 8 macrocell 41 pt glb2 generic logic block 8 macrocell 41 pt glb3 generic logic block 8 macrocell 41 pt h v out[1..2], out[3.. 8 ] out[9..14] 41 41 41
lattice semiconductor isppac-powr1014/a data sheet 20 figure 10. isppac-powr1014/a macrocell block diagram clock and timer functions figure 11 shows a block diagram of the isppac-powr1014/as internal clock and timer systems. the master clock operates at a ?ed frequency of 8mhz, from which a ?ed 250khz pld clock is derived. figure 11. clock and timer system the internal oscillator runs at a ?ed frequency of 8 mhz. this signal is used as a source for the pld and timer clocks. it is also used for clocking the comparator outputs and clocking the digital ?ters in the voltage monitor cir- pt0 pt1 pt2 pt3 pt4 d/t q r p to pld output clk clock polarity macrocell flip-flop provides d, t, or combinatorial output with polarity product term allocation global reset power on reset global polarity fuse for init product term block init product term internal oscillator 8 mhz 32 timer 0 timer 1 timer 3 timer 2 mclk pldclk pld c lock s w 0 s w 1 s w 2 to/from pld
lattice semiconductor isppac-powr1014/a data sheet 21 cuits and adc. the isppac-powr1014/a can be programmed to operate in three modes: master mode, standal- one mode and slave mode. table 5 summarizes the operating modes of isppac-powr1014/a. table 5. isppac-powr1014/a operating modes a divide-by-32 prescaler divides the internal 8mhz oscillator (or external clock, if selected) down to 250khz for the pld clock and for the programmable timers. this pld clock may be made available on the pldclk pin by closing sw2. each of the four timers provides independent timeout intervals ranging from 32? to 1.96 seconds in 128 steps. digital outputs the isppac-powr1014/a provides 14 digital outputs, hvout[1:2] and out[3:14]. outputs out[3:14] are perma- nently con?ured as open drain to provide a high degree of ?xibility when interfacing to logic signals, leds, opto- couplers, and power supply control inputs. the hvout[1:2] pins can be con?ured as either high voltage fet driv- ers or open drain outputs. each of these outputs may be controlled either from the pld or from the i 2 c bus (isp- pac-powr1014a only). the determination whether a given output is under pld or i 2 c control may be made on a pin-by-pin basis (see figure 12). for further details on controlling the outputs through i 2 c, please see the i 2 c/ smbus interface section of this data sheet. figure 12. digital output pin con?uration high-voltage outputs in addition to being usable as digital open-drain outputs, the isppac-powr1014/as hvout1-hvout2 output pins can be programmed to operate as high-voltage fet drivers. figure 13 shows the details of the hvout gate drivers. each of these outputs may be controlled from the pld, or with the isppac-powr1014a, from the i 2 c bus (see figure 13). for further details on controlling the outputs through i 2 c, please see the i 2 c/smbus interface sec- tion of this data sheet. timer operating mode sw0 sw1 condition comments standalone closed open when only one isppac-powr1014/a is used. mclk pin tristated master closed closed when more than one isppac-powr1014/a is used in a board, one of them should be con?ured to operate in this mode. mclk pin outputs 8mhz clock slave open closed when more than one isppac-powr1014/as is used in a board. other than the master, the rest of the isppac-powr1014/as should be pro- grammed as slaves. mclk pin is input outx pin digital control from pld digital control from i 2 c register (isppac-po w r1014a only)
lattice semiconductor isppac-powr1014/a data sheet 22 figure 13. basic function diagram for an output in high voltage mosfet gate driver mode figure 13 shows the hvout circuitry when programmed as a fet driver. in this mode the output either sources current from a charge pump or sinks current. the maximum voltage that the output level at the pin will rise to is also programmable between 6v and 10v. the maximum voltage levels that are required depend on the gate-to-source threshold of the fet being driven and the power supply voltage being switched. the maximum voltage level needs to be suf?ient to bias the gate-to-source threshold on and also accommodate the load voltage at the fets source, since the source pin of the fet to provide a wide range of ramp rates is tied to the supply of the target board. when the hvout pin is sourcing current, charging a fet gate, the source current is programmable between 12.5? and 100?. when the driver is turned to the off state, the driver will sink current to ground, and this sink current is also programmable between 3000? and 100? to control the turn-off rate. programmable output voltage levels for hvout1- hvout2 there are three selectable steps for the output voltage of the fet drivers when in fet driver mode. the voltage that the pin is capable of driving to can be programmed from 6v to 10v in 2v steps. resetb signal, reset command via jtag or i 2 c activating the resetb signal (logic 0 applied to the resetb pin) or issuing a reset instruction via jtag, or with the isppac-powr1014a, i 2 c will force the outputs to the following states independent of how these outputs have been con?ured in the pi n s window: out3-14 will go high-impedance. hvout pins programmed for open drain operation will go high-impedance. hvout pins programmed for fet driver mode operation will pull down. at the conclusion of the reset event, these outputs will go to the states de?ed by the pi n s window, and if a sequence has been programmed into the device, it will be re-started at the ?st step. the analog calibration will be re-done and consequently, the vmo n s, and adcs will not be operational until 500 microseconds (max.) after the conclusion of the reset event. caution: activating the resetb signal or issuing a reset command through i2c or jtag during the isppac- powr1014/a device operation, results in the device aborting all operations and returning to the power-on reset state. the status of the power supplies which are being enabled by the isppac-powr1014/a will be determined by the state of the outputs shown above. i source (12.5 to 100 a) i sink (100 to 500 a) +fast t u rn-off (3000 a) charge p u mp (6 to 10 v ) inp u t s u pply load h v outx pin digital control from pld digital control from i 2 c register (isppac-po w r1014a only) + -
lattice semiconductor isppac-powr1014/a data sheet 23 i 2 c/smbus interface (isppac-powr1014a only) i 2 c and smbus are low-speed serial interface protocols designed to enable communications among a number of devices on a circuit board. the isppac-powr1014a supports a 7-bit addressing of the i 2 c communications proto- col, as well as smbtimeout and smbalert features of the smbus, enabling it to easily integrated into many types of modern power management systems. figure 14 shows a typical i 2 c con?uration, in which one or more isppac- powr1014as are slaved to a supervisory microcontroller. sda is used to carry data signals, while scl provides a synchronous clock signal. the smbalert line is only present in smbus systems. the 7-bit i 2 c address of the powr1014a is fully programmable through the jtag port. figure 14. isppac-powr1014a in i 2 c/smbus system in both the i 2 c and smbus protocols, the bus is controlled by a single master device at any given time. this mas- ter device generates the scl clock signal and coordinates all data transfers to and from a number of slave devices. the isppac-powr1014a is con?ured as a slave device, and cannot independently coordinate data transfers. each slave device on a given i 2 c bus is assigned a unique address. the isppac-powr1014a implements the 7-bit addressing portion of the standard. any 7-bit address can be assigned to the isppac-powr1014a device by pro- gramming through jtag. when selecting a device address, one should note that several addresses are reserved by the i 2 c and/or smbus standards, and should not be assigned to isppac-powr1014a devices to assure bus compatibility. table 6 lists these reserved addresses. table 6. i 2 c/smbus reserved slave device addresses address r/w bit i 2 c function description smbus function 0000 000 0 general call address general call address 0000 000 1 start byte start byte 0000 001 x cbus address cbus address 0000 010 x reserved reserved 0000 011 x reserved reserved 0000 1xx x hs-mode master code hs-mode master code 0001 000 x n a smbus host 0001 100 x n a smbus alert response address 0101 000 x n a reserved for access.bus 0110 111 x n a reserved for access.bus 1100 001 x n a smbus device default address 1111 0xx x 10-bit addressing 10-bit addressing 1111 1xx x reserved reserved microprocessor (i 2 c master) powr1014a (i 2 c slave) powr1014a (i 2 c slave) sda sda sda scl scl scl scl/smclk (clock) sda/smdat (data) smbalert out5/ smba out5/ smba to other i 2 c devices interrupt v+
lattice semiconductor isppac-powr1014/a data sheet 24 the isppac-powr1014as i 2 c/smbus interface allows data to be both written to and read from the device. a data write transaction (figure 15) consists of the following operations: 1. start the bus transaction 2. transmit the device address (7 bits) along with a low write bit 3. transmit the address of the register to be written to (8 bits) 4. transmit the data to be written (8 bits) 5. stop the bus transaction to start the transaction, the master device holds the scl line high while pulling sda low. address and data bits are then transferred on each successive scl pulse, in three consecutive byte frames of 9 scl pulses. address and data are transferred on the ?st 8 scl clocks in each frame, while an acknowledge signal is asserted by the slave device on the 9th clock in each frame. both data and addresses are transferred in a most-signi?ant-bit-?st format. the ?st frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. the second frame contains the register address to which data will be written, and the ?al frame contains the actual data to be writ- ten. n ote that the sda signal is only allowed to change when the scl is low, as raising sda when scl is high sig- nals the end of the transaction. figure 15. i 2 c write operation reading a data byte from the isppac-powr1014a requires two separate bus transactions (figure 16). the ?st transaction writes the register address from which a data byte is to be read. n ote that since no data is being written to the device, the transaction is concluded after the second byte frame. the second transaction performs the actual read. the ?st frame contains the 7-bit device address with the r/w bit held high. in the second frame the isppac- powr1014a asserts data out on the bus in response to the scl signal. n ote that the acknowledge signal in the second frame is asserted by the master device and not the isppac-powr1014a. figure 16. i 2 c read operation the isppac-powr1014a provides 17 registers that can be accessed through its i 2 c interface. these registers provide the user with the ability to monitor and control the devices inputs and outputs, and transfer data to and from the device. table 7 provides a summary of these registers. ack ack ack start 123456789 a6 a5 a4 a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 123456789 123456789 d7 d6 d5 d4 d3 d2 d1 d0 stop device address (7 bits) register address (8 bits) write data (8 bits) scl sda r/w note: shaded bits asserted by slave d5 d4 d3 d2 d1 d0 d6 d7 ack ack ack start 123456789 a6 a5 a4 a3 a2 a1 a0 r7 r6 r5 r4 r3 r2 r1 r0 123456789 device address (7 bits) register address (8 bits) scl sda r/w stop start 123456789 a6 a5 a4 a3 a2 a1 a0 ack 123456789 device address (7 bits) read data (8 bits) scl sda r/w stop step 1: write register address for read operation step 2: read data from that register note: shaded bits asserted by slave optional
lattice semiconductor isppac-powr1014/a data sheet 25 table 7. i 2 c control registers several registers are provided for monitoring the status of the analog inputs. the three registers vmo n _status[0:2] provide the ability to read the status of the vmo n output comparators. the ability to read both the ? and ? comparators from each vmo n input is provided through the vmo n input registers. n ote that if a vmo n input is con?ured to window comparison mode, then the corresponding vmo n xa register bit will re?ct the status of the window comparison. figure 17. vmon status registers it is also possible to directly read the value of the voltage present on any of the vmo n inputs by using the isppac- powr1014as adc. three registers provide the i 2 c interface to the adc (figure 18). register address register name read/write description value after por 1, 2 0x00 vmon_status0 r vmo n input status vmon[4:1] ??? ??? 0x01 vmon_status1 r vmo n input status vmon[8:5] ??? ??? 0x02 vmon_status2 r vmo n input status vmon[10:9] x x x x ??? 0x03 output_status0 r output status out[8:3], hvout[2:1] ??? ??? 0x04 output_status1 r output status out[14:9] x x ? ??? 0x06 input_status r input status i n [4:1] x x x x ??? 0x07 adc_value_low r adc d[3:0] and status ??? x x x 1 0x08 adc_value_high r adc d[9:4] x x ? ??? 0x09 adc_mux r/w adc attenuator and mux[3:0] x x x 1 1 1 1 1 0x0a ues_byte0 r ues[7:0] ??? ??? 0x0b ues_byte1 r ues[15:8] ??? ??? 0x0c ues_byte2 r ues[23:16] ??? ??? 0x0d ues_byte3 r ues[31:24] ??? ??? 0x0e gp_output1 r/w gpout[8:1] 0 0 0 0 0 1 0 0 0x0f gp_output2 r/w gpout[14:9] x x 0 0 0 0 0 0 0x11 input_value r/w pld input state [4:2] x x x x ???x 0x12 reset w resets device on write n /a 1. ? = n on-functional bit (bits read out as 1s). 2. = state depends on device con?uration or input status. vmon4b vmon4a vmon3b vmon3a vmon2b vmon2a vmon1b vmon1a b7 b0 0x00 - vmon_status0 (read only) b6 b5 b4 b3 b2 b1 vmon8b vmon8a vmon7b vmon7a vmon6b vmon6a vmon5b vmon5a b7 b0 0x01 - vmon_status1 (read only) b6 b5 b4 b3 b2 b1 vmon10b vmon10a vmon9b vmon9a 1111 b7 b0 0x02 - vmon_status2 (read only) b6 b5 b4 b3 b2 b1
lattice semiconductor isppac-powr1014/a data sheet 26 figure 18. adc interface registers to perform an a/d conversion, one must set the input attenuator and channel selector. two input ranges may be set using the attenuator, 0 - 2.048v and 0 - 6.144v. table 8 shows the input attenuator settings. table 8. adc input attenuator control the input selector may be set to monitor any one of the ten vmo n inputs, the vcca input, or the vcci n p input. table 9 shows the codes associated with each input selection. table 9. v mon address selection table writing a value to the adc_mux register to set the input attenuator and selector will automatically initiate a conver- sion. when the conversion is in process, the do n e bit (adc_value_low.0) will be reset to 0. when the conver- sion is complete, this bit will be set to 1. when the conversion is complete, the result may be read out of the adc by performing two i 2 c read operations; one for adc_value_low, and one for adc_value_high. it is recom- mended that the i 2 c master load a second conversion command only after the completion of the current conversion atten (adc_mux.4) resolution full-scale range 0 2mv 2.048 v 1 6mv 6.144 v select word input channel sel3 (adc_mux.3) sel2 (adc_mux.2) sel1 (adc_mux.1) sel0 (adc_mux.0) 0000vmo n 1 0001vmo n 2 0010vmo n 3 0011vmo n 4 0100vmo n 5 0101vmo n 6 0110vmo n 7 0111vmo n 8 1000vmo n 9 1001vmo n 10 1100 vcca 1101 vcci n p d3 d2 d1 d0 1 1 1 done b7 b0 0x07 - adc_value_low (read only) b6 b5 b4 b3 b2 b1 d11 d10 d9 d8 d7 d6 d5 d4 b7 b0 0x08 - adc_value_high (read only) b6 b5 b4 b3 b2 b1 x x x atten sel3 sel2 sel1 sel0 b7 b0 0x09 - adc_mux (read/write) b6 b5 b4 b3 b2 b1
lattice semiconductor isppac-powr1014/a data sheet 27 command (waiting for the do n e bit to be set to 1). an alternative would be to wait for a minimum speci?d time (see t co n vert value in the speci?ations) and disregard checking the do n e bit. n ote that if the i 2 c clock rate falls below 50khz (see f i 2 c note in speci?ations), the only way to insure a valid adc conversion is to wait the minimum speci?d time (t co n vert ), as the operation of the do n e bit at clock rates lower than that cannot be guaranteed. in other words, if the i 2 c clock rate is less than 50khz, the do n e bit may or may not assert even though a valid conversion result is available. to insure every adc conversion result is valid, preferred operation is to clock i 2 c at more than 50khz and verify do n e bit status or wait for the full t co n vert time period between subsequent adc convert commands. if an i 2 c request is placed before the current conversion is complete, the do n e bit will be set to 1 only after the second request is complete. the status of the digital input lines may also be monitored and controlled through i 2 c commands. figure 19 shows the i 2 c interface to the i n [1:4] digital input lines. the input status may be monitored by reading the i n put_status register, while input values to the pld array may be set by writing to the i n put_value register. to be able to set an input value for the pld array, the input multiplexer associated with that bit needs to be set to the i 2 c register set- ting in e 2 cmos memory otherwise the pld will receive its input from the i n x pin. figure 19. i 2 c digital input interface the digital outputs may also be monitored and controlled through the i 2 c interface, as shown in figure 20. the sta- tus of any given digital output may be read by reading the contents of the associated output_status[1:0] regis- ter. n ote that in the case of the outputs, the status re?cted by these registers re?cts the logic signal used to drive the pin, and does not sample the actual level present on the output pin. for example, if an output is set high but is input_status input_value 3 3 3 pld array i 2 c interface unit in[2..4] in1 userjtag bit 2 3 pld o utput / input_value register s elect (e 2 configuration) in4 in3 in2 in1 1111 b7 b0 0x06 - input_status (read only) b6 b5 b4 b3 b2 b1 xxx x b7 b0 0x11 - input_value (read/write) b6 b5 b4 b3 b2 b1 mux mux i4 i3 i2 x
lattice semiconductor isppac-powr1014/a data sheet 28 not pulled up, the output status bit corresponding with that pin will read ?? but a high output signal will not appear on the pin. digital outputs may also be optionally controlled directly by the i 2 c bus instead of by the pld array. the outputs may be driven either from the pld output or from the contents of the gp_output[1:0] registers with the choice user-settable in e 2 cmos memory. each output may be independently set to output from the pld or from the gp_output registers. figure 20. i 2 c output monitor and control logic the ues word may also be read through the i 2 c interface, with the register mapping shown in figure 21. output_status0 output_status1 gp_output1 gp_output2 14 14 hvout[1..2] out[3..14] i 2 c interface unit pld output/gp_output register select (e 2 configuration) out8 out7 out6 out5 hvout2 hvout1 out4 11 out3 b7 b0 0x03 - output_status0 (read only) b6 b5 b4 b3 b2 b1 out14 out13 out12 out11 out10 out9 b7 b0 0x04 - output_status1 (read only) b6 b5 b4 b3 b2 b1 gp8 gp7 gp6 gp5 gp4 gp3_enb gp2 gp1 b7 b0 0x0e - gp_output1 (read/write) b6 b5 b4 b3 b2 b1 x x gp14 gp13 gp12 gp11 gp10 gp9 b7 b0 0x0f - gp_output2 (r ead/write) b6 b5 b4 b3 b2 b1 14 14 14 mux pld output routin g pool
lattice semiconductor isppac-powr1014/a data sheet 29 figure 21. i 2 c register mapping for ues bits the i 2 c interface also provides the ability to initiate reset operations. the isppac-powr1014a may be reset by issuing a write of any value to the i 2 c reset register (figure 22). n ote: the execution of the i 2 c reset command is equivalent to toggling the resetb pin of the chip. refer to the resetb signal, reset command via jtag or i 2 c section of this data sheet for further information. figure 22. i 2 c reset register ues7 ues6 ues5 ues4 ues3 ues2 ues1 ues0 b7 b0 0x0a - ues_byte0 (read only) b6 b5 b4 b3 b2 b1 ues15 ues14 ues13 ues12 ues11 ues10 ues9 ues8 b7 b0 0x0b - ues_byte1 (read only) b6 b5 b4 b3 b2 b1 ues23 ues22 ues21 ues20 ues19 ues18 ues17 ues16 b7 b0 0x0c - ues_byte2 (read only) b6 b5 b4 b3 b2 b1 ues31 ues30 ues29 ues28 ues27 ues26 ues25 ues24 b7 b0 0x0d - ues_byte3 (read only) b6 b5 b4 b3 b2 b1 xxxxxxxx b7 b0 0x12 - reset (write only) b6 b5 b4 b3 b2 b1
lattice semiconductor isppac-powr1014/a data sheet 30 smbus smbalert function the isppac-powr1014a provides an smbus smbalert function so that it can request service from the bus mas- ter when it is used as part of an smbus system. this feature is supported as an alternate function of out3. when the smbalert feature is enabled, out3 is controlled by a combination of the pld output and the gp3_e n b bit (figure 23). n ote: to enable the smbalert feature, the smb_mode (eecmos bit) should be set in software. figure 23. isppac-powr1014/a smbalert logic the typical ?w for an smbalert transaction is as follows (figure 23): 1. gp3_e n b bit is forced (via i 2 c write) to low 2. isppac-powr1014a pld logic pulls out3/smba low 3. master responds to interrupt from smba line 4. master broadcasts a read operation using the smbus alert response address (ara) 5. isppac-powr1014a responds to read request by transmitting its device address 6. if transmitted device address matches isppac-powr1014a address, it sets gp3_e n b bit high. this releases out3/smba. figure 24. smbalert bus transaction after out3/smba has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the isppac-powr1014a. as part of the service functions, the bus master will typically need to clear whatever condition initiated the smbalert request, and will also need to reset gp3_e n b to re-enable the smbalert function. for further information on the smbus, the user should consult the smbus standard. pld output routin g pool mux mux gp3_enb smbalert lo g ic out3/smba i 2 c interface unit pld o u tp u t/gp_o u tp u t register select (e 2 config u ration) out3/smba mode select (e 2 config u ration) ack a4 a3 a2 a1 a0 x a5 a6 start 123456789 000110 0 ack 123456789 alert response address (0001 100) slave address (7 bits) scl sda r/w stop smba note: shaded bits asserted by slave slave asserts smba slave releases smba
lattice semiconductor isppac-powr1014/a data sheet 31 software-based design environment designers can con?ure the isppac-powr1014/a using pac-designer, an easy to use, microsoft windows com- patible program. circuit designs are entered graphically and then veri?d, all within the pac-designer environment. full device programming is supported using pc parallel port i/o operations and a download cable connected to the serial programming interface pins of the isppac-powr1014/a. a library of con?urations is included with basic solutions and examples of advanced circuit techniques are available on the lattice web site for downloading. in addition, comprehensive on-line and printed documentation is provided that covers all aspects of pac-designer operation. the pac-designer schematic window, shown in figure 25, provides access to all con?urable isppac- powr1014/a elements via its graphical user interface. all analog input and output pins are represented. static or non-con?urable pins such as power, ground, and the serial digital interface are omitted for clarity. any element in the schematic window can be accessed via mouse operations as well as menu commands. when completed, con- ?urations can be saved, simulated, and downloaded to devices. figure 25. pac-designer isppac-powr1014/a design entry screen in-system programming the isppac-powr1014/a is an in-system programmable device. this is accomplished by integrating all e 2 con?- uration memory and control logic on-chip. programming is performed through a 4-wire, ieee 1149.1 compliant serial jtag interface at normal logic levels. once a device is programmed, all con?uration information is stored on-chip, in non-volatile e 2 cmos memory cells. the speci?s of the ieee 1149.1 serial interface and all isppac- powr1014/a instructions are described in the jtag interface section of this data sheet. programming isppac-powr1014/a: alternate method some applications require that the isppac-powr1014/a be programmed before turning the power on to the entire circuit board. to meet such application needs, the isppac-powr1014/a provides an alternate programming method which enables the programming of the isppac-powr1014/a device through the jtag chain with a sepa- rate power supply applied just to the programming section of the isppac-powr1014/a device with the main power supply of the board turned off.
lattice semiconductor isppac-powr1014/a data sheet 32 three special purpose pins, vccprog, atdi and tdisel, enable programming of the un-programmed isppac- powr1014/a under such circumstances. the vccprog pin powers just the programming circuitry of the isppac- powr1014/a device. the atdi pin provides an alternate connection to the jtag header while bypassing all the un-powered devices in the jtag chain. tdisel pin enables switching between the atdi and the standard jtag signal tdi. when the internally pulled-up tdisel = 1, standard tdi pin is enabled and when the tdisel = 0, atdi is enabled. in order to use this feature the jtag signals of the isppac-powr1014/a are connected to the header as shown in figure 26. n ote: the isppac-powr1014/a should be the last device in the jtag chain. figure 26. isppac-powr1014/a alternate tdi con?uration diagram alternate tdi selection via jtag command when the tdisel pin held high and four consecutive idcode instructions are issued, isppac-powr1014/a responds by making its active jtag data input the atdi pin. when atdi is selected, data on its tdi pin is ignored until the jtag state machine returns to the test-logic-reset state. this method of selecting atdi takes advantage of the fact that a jtag device with an idcode register will auto- matically load its unique idcode instruction into the instruction register after a test-logic-reset. this jtag capa- bility permits blind interrogation of devices so that their location in a serial chain can be identi?d without having to know anything about them in advance. a blind interrogation can be made using only the tms and tclk control pins, which means tdi and tdo are not required for performing the operation. figure 27 illustrates the logic for selecting whether the tdi or atdi pin is the active data input to isppac-powr1014/a. tdi atdi tck tdo tms tdi tck tdo tms tdi tck tms v cc v cc v ccio v ccj tdisel tdo tdisel v ccprog 2. initial po w er s u pply t u rn-on 3. se qu enced po w er s u pply t u rn-on jtag signal connector other jtag device(s) isppac-powr 1014a 1. po w er for programming po w r1014a v ccj
lattice semiconductor isppac-powr1014/a data sheet 33 figure 27. isppac-powr1014/a tdi/atdi pin selection diagram table 10 shows in truth table form the same conditions required to select either tdi or atdi as in the logic diagram found in figure 27. table 10. isppac-powr1014/a atdi/tdi selection table please refer to the lattice application note a n 6068, programming the isppac-powr1220at8 in a jtag chain using atdi . the application note includes speci? svf code examples and information on the use of lattice design tools to verify device operation in alternate tdi mode. vccprog power supply pin because the vccprog pin directly powers the on-chip programming circuitry, the isppac-powr1014/a device can be programmed by applying power to the vccprog pin (without powering the entire chip though the vccd and vcca pins). in addition, to enable the on-chip jtag interface circuitry, power should be applied to the vccj pin. when the isppac-powr1014/a is using the vccprog pin, its vccd and vcca pins can be open or pulled low. additionally, other than jtag i/o pins, all digital output pins are in hi-z state, hvout pins con?ured as mosfet driver are driven low, and all other inputs are ignored. to switch the power supply back to vccd and vcca pins, one should turn the vccprog supply and vccj off before turning the regular supplies on. user electronic signature a user electronic signature (ues) feature is included in the e 2 cmos memory of the isppac-powr1014/a. this consists of 32 bits that can be con?ured by the user to store unique data such as id codes, revision numbers or tdisel pin jtag state machine test-logic-reset 4 consecutive idcode commands loaded at update-ir active jtag data input pin h n o yes atdi (tdi disabled) hyes n o tdi (atdi disabled) l x x atdi (tdi disabled) 1 0 tdi atdi tdisel q set clr test-logic-reset 4 consec u ti v e idcode instr u ctions loaded at update-ir tdo tms tck jtag isppac-powr1014/a
lattice semiconductor isppac-powr1014/a data sheet 34 inventory control data. the speci?s of this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. electronic security an electronic security ?use (esf) bit is provided in every isppac-powr1014/a device to prevent unauthorized readout of the e 2 cmos con?uration bit patterns. once programmed, this cell prevents further access to the func- tional user bits in the device. this cell can only be erased by reprogramming the device, so the original con?ura- tion cannot be examined once programmed. usage of this feature is optional. the speci?s of this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. production programming support once a ?al con?uration is determined, an ascii format jedec ?e can be created using the pac-designer soft- ware. devices can then be ordered through the usual supply channels with the users speci? con?uration already preloaded into the devices. by virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and ?xibility in production planning. evaluation fixture because the features of an isppac-powr1014/a are all included in the larger isppac-powr1220at8 device, designs implemented in an isppac-powr1014/a can be veri?d using an isppac-powr1220at8 engineering prototype board connected to the parallel port of a pc with a lattice ispdow n load cable. the board demon- strates proper layout techniques and can be used in real time to check circuit operation as part of the design pro- cess. input and output connections are provided to aid in the evaluation of the functionality implemented in isppac- powr1014/a for a given application. (figure 28). figure 28. download from a pc ieee standard 1149.1 interface (jtag) serial port programming interface communication with the isppac-powr1014/a is facilitated via an ieee 1149.1 test access port (tap). it is used by the isppac-powr1014/a as a serial programming interface. a brief descrip- tion of the isppac-powr1014/a jtag interface follows. for complete details of the reference speci?ation, refer to the publication, standard test access port and boundary-scan architecture, ieee std 1149.1-1990 (which now includes ieee std 1149.1a-1993). overview an ieee 1149.1 test access port (tap) provides the control interface for serially accessing the digital i/o of the isp- pac-powr1014/a. the tap controller is a state machine driven with mode and clock inputs. given in the correct sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. device programming is performed by addressing the con?uration register, shifting data in, and then executing a program con?uration instruction, after which the data is transferred to internal e 2 cmos cells. it is these non-volatile cells that store the con?uration or the isppac-powr1014/a. a set of ispdow n load cable (6') 4 other system circuitry isppac-powr 1220at8 device pac-designer software
lattice semiconductor isppac-powr1014/a data sheet 35 instructions are de?ed that access all data registers and perform other internal control operations. for compatibil- ity between compliant devices, two data registers are mandated by the ieee 1149.1 speci?ation. others are func- tionally speci?d, but inclusion is strictly optional. finally, there are provisions for optional data registers de?ed by the manufacturer. the two required registers are the bypass and boundary-scan registers. figure 29 shows how the instruction and various data registers are organized in an isppac-powr1014/a. figure 29. isppac-powr1014/a tap registers tap controller speci?s the tap is controlled by the test clock (tck) and test mode select (tms) inputs. these inputs determine whether an instruction register or data register operation is performed. driven by the tck input, the tap consists of a small 16-state controller design. in a given state, the controller responds according to the level on the tms input as shown in figure 30. test data in (tdi) and tms are latched on the rising edge of tck, with test data out (tdo) becoming valid on the falling edge of tck. there are six steady states within the controller: test-logic-reset, run- test/idle, shift-data-register, pause-data-register, shift-instruction-register and pause-instruction-register. but there is only one steady state for the condition when tms is set high: the test-logic-reset state. this allows a reset of the test logic within ?e tcks or less by keeping the tms input high. test-logic-reset is the power-on default state. address register (109 bits) e 2 cmos n o n -volatile memory ues register (32 bits) idcode register (32 bits) bypass register (1 bit) i n structio n register (8 bits) test access port (tap) logic output latch tdi tck tms tdo cfg address register (12 bits) multiplexer data register (123 bits) cfg data register (56 bits)
lattice semiconductor isppac-powr1014/a data sheet 36 figure 30. tap states when the correct logic sequence is applied to the tms and tck inputs, the tap will exit the test-logic-reset state and move to the desired state. the next state after test-logic-reset is run-test/idle. until a data or instruction shift is performed, no action will occur in run-test/idle (steady state = idle). after run-test/idle, either a data or instruc- tion shift is performed. the states of the data and instruction register blocks are identical to each other differing only in their entry points. when either block is entered, the ?st action is a capture operation. for the data regis- ters, the capture-dr state is very simple: it captures (parallel loads) data onto the selected serial data path (previ- ously chosen with the appropriate instruction). for the instruction register, the capture-ir state will always load the idcode instruction. it will always enable the id register for readout if no other instruction is loaded prior to a shift-dr operation. this, in conjunction with mandated bit codes, allows a ?lind interrogation of any device in a compliant ieee 1149.1 serial chain. from the capture state, the tap transitions to either the shift or exit1 state. n ormally the shift state follows the capture state so that test data or status information can be shifted out or new data shifted in. following the shift state, the tap either returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the pause state is used to temporarily suspend the shifting of data through either the data or instruction register while an external operation is performed. from the pause state, shifting can resume by reentering the shift state via the exit2 state or be terminated by entering the run-test/idle state via the exit2 and update states. if the proper instruction is shifted in during a shift-ir operation, the next entry into run-test/idle initiates the test mode (steady state = test). this is when the device is actually programmed, erased or veri?d. all other instructions are executed in the update state. test instructions like data registers, the ieee 1149.1 standard also mandates the inclusion of certain instructions. it outlines the function of three required and six optional instructions. any additional instructions are left exclusively for the manu- facturer to determine. the instruction word length is not mandated other than to be a minimum of two bits, with only the bypass and extest instruction code patterns being speci?ally called out (all ones and all zeroes respec- tively). the isppac-powr1014/a contains the required minimum instruction set as well as one from the optional instruction set. in addition, there are several proprietary instructions that allow the device to be con?ured and ver- i?d. table 11 lists the instructions supported by the isppac-powr1014/a jtag test access port (tap) controller: test-logic-rst run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 00 00 00 11 00 00 11 11 00 11 00 11 11 11 1 0 n ote: the value shown adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck.
lattice semiconductor isppac-powr1014/a data sheet 37 table 11. isppac-powr1014/a tap instruction table bypass is one of the three required instructions. it selects the bypass register to be connected between tdi and tdo and allows serial data to be transferred through the device without affecting the operation of the isppac- powr1014/a. the ieee 1149.1 standard de?es the bit code of this instruction to be all ones (11111111). the required sample/preload instruction dictates the boundary-scan register be connected between tdi and tdo. the isppac-powr1014/a has no boundary scan register, so for compatibility it defaults to the bypass mode whenever this instruction is received. the bit code for this instruction is de?ed by lattice as shown in table 11. the extest (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between tdi and tdo. again, since the isppac-powr1014/a has no boundary scan logic, the device is put in the bypass mode to ensure speci?ation compatibility. the bit code of this instruction is de?ed by the 1149.1 standard to be all zeros (00000000). instruction command code comments bulk_erase 0000 0011 bulk erase device bypass 1111 1111 bypass - connect tdo to tdi discharge 0001 0100 fast vpp discharge erase_do n e_bit 0010 0100 erases ?one bit only extest 0000 0000 bypass - connect tdo to tdi idcode 0001 0110 read contents of manufacturer id code (32 bits) outputs_highz 0001 1000 force all outputs to high-z state, fet outputs pulled low sample/preload 00011100 sample/preload. default to bypass. program_disable 0001 1110 disable program mode program_do n e_bit 0010 1111 programs the done bit program_e n able 0001 0101 enable program mode program_security 0000 1001 program security fuse reset 0010 0010 resets device (refer to the resetb signal, reset command via jtag or i 2 c section of this data sheet) i n 1_reset_jtag_bit 0001 0010 reset the jtag bit associated with i n 1 pin to 0 i n 1_set_jtag_bit 0001 0011 set the jtag bit associated with i n 1 pin to 1 cfg_address 0010 1011 select non-pld address register cfg_data_shift 0010 1101 n on-pld data shift cfg_erase 0010 1001 erase just the n on pld con?uration cfg_program 0010 1110 n on-pld program cfg_verify 0010 1000 vrify non-pld fusemap data pld_address_shift 0000 0001 pld_address register (109 bits) pld_data_shift 0000 0010 pld_data register (123 bits) pld_i n it_addr_for_prog_i n cr 0010 0001 initialize the address register for auto increment pld_prog_i n cr 0010 0111 program column register to e 2 and auto increment address register pld_program 0000 0111 program pld data register to e 2 pld_verify 0000 1010 veri?s pld column data pld_verify_i n cr 0010 1010 load column register from e 2 and auto increment address register ues_program 0001 1010 program ues bits into e 2 ues_read 0001 0111 read contents of ues register from e 2 (32 bits)
lattice semiconductor isppac-powr1014/a data sheet 38 the optional idcode (identi?ation code) instruction is incorporated in the isppac-powr1014/a and leaves it in its functional mode when executed. it selects the device identi?ation register to be connected between tdi and tdo. the identi?ation register is a 32-bit shift register containing information regarding the ic manufacturer, device type and version code (figure 31). access to the identi?ation register is immediately available, via a tap data scan operation, after power-up of the device, or by issuing a test-logic-reset instruction. the bit code for this instruction is de?ed by lattice as shown in table 11. figure 31. isppac-powr1014/a id code isppac-powr1014/a speci? instructions there are 25 unique instructions speci?d by lattice for the isppac-powr1014/a. these instructions are primarily used to interface to the various user registers and the e 2 cmos non-volatile memory. additional instructions are used to control or monitor other features of the device. a brief description of each unique instruction is provided in detail below, and the bit codes are found in table 11. pld_address_shift ?this instruction is used to set the address of the pld a n d/arch arrays for subsequent program or read operations. this instruction also forces the outputs into the outputs_highz. pld_data_shift ?this instruction is used to shift pld data into the register prior to programming or reading. this instruction also forces the outputs into the outputs_highz. pld_init_addr_for_prog_incr ?this instruction prepares the pld address register for subsequent pld_prog_i n cr or pld_verify_i n cr instructions. pld_prog_incr ?this instruction programs the pld data register for the current address and increments the address register for the next set of data. pld_program ?this instruction programs the selected pld a n d/arch array column. the speci? column is preselected by using pld_address_shift instruction. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_e n able instruction). this instruction also forces the outputs into the outputs_highz. program_security ?this instruction is used to program the electronic security fuse (esf) bit. programming the esf bit protects proprietary designs from being read out. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_e n able instruction). this instruction also forces the outputs into the outputs_highz. pld_verify ?this instruction is used to read the content of the selected pld a n d/arch array column. this speci? column is preselected by using pld_address_shift instruction. this instruction also forces the outputs into the outputs_highz. discharge ?this instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares isppac-powr1014/a for a read cycle. this instruction also forces the outputs into the outputs_highz. 0000 0000 0001 0100 0101 / 0000 0100 001 / 1 (isppac-powr1014a) 0001 0000 0001 0100 0101 / 0000 0100 001 / 1 (isppac-powr1014) msb lsb part n umber (20 bits) 00145h = isppac-powr1014a 10145h = isppac-powr1014 jedec manufacturer identity code for lattice semiconductor (11 bits) constant 1 (1 bit) per 1149.1-1990
lattice semiconductor isppac-powr1014/a data sheet 39 cfg_address ?this instruction is used to set the address of the cfg array for subsequent program or read operations. this instruction also forces the outputs into the outputs_highz. cfg_data_shift ?this instruction is used to shift data into the cfg register prior to programming or reading. this instruction also forces the outputs into the outputs_highz. cfg_erase ?this instruction will bulk erase the cfg array. the action occurs at the second rising edge of tck in run-test-idle jtag state. the device must already be in programming mode (program_e n able instruction). this instruction also forces the outputs into the outputs_highz. cfg_program ?this instruction programs the selected cfg array column. this speci? column is preselected by using cfg_address instruction. the programming occurs at the second rising edge of the tck in run-test- idle jtag state. the device must already be in programming mode (program_e n able instruction). this instruction also forces the outputs into the outputs_highz. cfg_verify ?this instruction is used to read the content of the selected cfg array column. this speci? column is preselected by using cfg_address instruction. this instruction also forces the outputs into the outputs_highz. bulk_erase ?this instruction will bulk erase all e 2 cmos bits (cfg, pld, ues, and esf) in the isppac- powr1014/a. the device must already be in programming mode (program_e n able instruction). this instruc- tion also forces the outputs into the outputs_highz. outputs_highz ?this instruction turns off all of the open-drain output transistors. pins that are programmed as fet drivers will be placed in the active low state. this instruction is effective after update-instruction-register jtag state. program_enable ?this instruction enables the programming mode of the isppac-powr1014/a. this instruction also forces the outputs into the outputs_highz. idcode ?this instruction connects the output of the identi?ation code data shift (idcode) register to tdo (figure 32), to support reading out the identi?ation code. figure 32. idcode register program_disable ?this instruction disables the programming mode of the isppac-powr1014/a. the test- logic-reset jtag state can also be used to cancel the programming mode of the isppac-powr1014/a. ues_read ?this instruction both reads the e 2 cmos bits into the ues register and places the ues register between the tdi and tdo pins (as shown in figure 29), to support programming or reading of the user electronic signature bits. figure 33. ues register ues_program ?this instruction will program the content of the ues register into the ues e 2 cmos memory. the device must already be in programming mode (program_e n able instruction). this instruction also forces the outputs into the outputs_highz. erase_done_bit ?this instruction clears the 'done' bit, which prevents the isppac-powr1014/a sequence from starting. tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 27 bit 28 bit 29 bit 30 bit 31 tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15
lattice semiconductor isppac-powr1014/a data sheet 40 program_done_bit ?this instruction sets the 'done' bit, which enables the isppac-powr1014/a sequence to start. reset ?this instruction resets the pld sequence and output macrocells. in1_reset_jtag_bit ?this instruction clears the jtag register logic input 'i n 1.' the pld input has to be con- ?ured to take input from the jtag register in order for this command to have effect on the sequence. in1_set_jtag_bit ?this instruction sets the jtag register logic input 'i n 1.' the pld input has to be con?ured to take input from the jtag register in order for this command to have effect on the sequence. pld_verify_incr ?this instruction reads out the pld data register for the current address and increments the address register for the next read. notes: in all of the descriptions above, outputs_highz refers both to the instruction and the state of the digital output pins, in which the open-drains are tri-stated and the fet drivers are pulled low. before any of the above programming instructions are executed, the respective e 2 cmos bits need to be erased using the corresponding erase instruction.
lattice semiconductor isppac-powr1014/a data sheet 41 package diagrams 48-pin tqfp (dimensions in millimeters) exact shape of each corner is optional. to the lowest point on the package body. 7. a1 is defined as the distance from the seating plane base metal lead between 0.10 and 0.25 mm from the lead tip. 1. dimensioning and tolerancing per ansi y14.5 - 1982. these dimensions apply to the flat section of the allowable mold protrusion is 0.254 mm on d1 and e1 datums a, b and d to be determined at datum plane h. 4. dimensions d1 and e1 do not include mold protrusion. 5. the top of package may be smaller than the bottom 8. of the package by 0.15 mm. dimensions. 2. all dimensions are in millimeters. 6. section b-b: 3. 1 b 0.22 0.17 b 0.27 0.16 0.23 0.20 0.09 c c1 0.09 b1 0.17 0.15 0.13 0.20 max. 1.60 0.15 0.75 1.45 e n l 0.45 0.50 bsc 0.60 48 e1 e d1 d 9.00 bsc 7.00 bsc 9.00 bsc 7.00 bsc a2 a1 1.35 0.05 symbol a- min. 1.40 - nom. - c a-b d see detail "a" lead finish c seating plane a 3. 0.08 c b 1 c mc b a-b d 3. d 4x 8. e b 3. e d 0.20 gauge plane a1 0.08 c aa2 1.00 ref. l 0.20 min. b 0-7 b h e1 0.25 0.20 d a-b h d1 section b - b detail "a" notes: pin 1 indicator 1 n
lattice semiconductor isppac-powr1014/a data sheet 42 part number description isppac-powr1014/a ordering information conventional packaging lead-free packaging part number package pins ISPPAC-POWR1014A-01T48I tqfp 48 isppac-powr1014-01t48i tqfp 48 part number package pins isppac-powr1014a-01t n 48i lead-free tqfp 48 isppac-powr1014-01t n 48i lead-free tqfp 48 device number isppac-powr1014x - 01xx48x operating temperature range i = industrial (-40 o c to +85 o c) package t = 48-pin tqfp t n = lead-free 48-pin tqfp* performance grade 01 = standard adc support a = adc present device family
lattice semiconductor isppac-powr1014/a data sheet 43 package options isppac-powr1014a 4 8 -pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 36 35 34 33 32 31 30 29 2 8 27 26 25 4 8 47 46 45 44 43 42 41 40 39 3 8 37 out14 out13 out12 out11 out10 out9 out 8 out7 out6 out5 out4 gndd v mon9 v mon 8 v mon7 v mon6 v mon5 gndd v cca v mon4 v mon3 v mon2 v mon1 gnda in4 in3 in2 v ccinp in1 mclk v ccd resetb scl sda v mon10 pldclk smba_out3 h v out2 h v out1 tms atdi tdi v ccj tdo tck v ccd v ccprog tdisel
lattice semiconductor isppac-powr1014/a data sheet 44 package options (cont.) technical support assistance hotline: 1-800-lattice ( n orth america) +1-503-268-8001 (outside n orth america) e-mail: isppacs@latticesemi.com internet: www .latticesemi.com isppac-powr1014 4 8 -pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 36 35 34 33 32 31 30 29 2 8 27 26 25 4 8 47 46 45 44 43 42 41 40 39 3 8 37 out14 out13 out12 out11 out10 out9 out 8 out7 out6 out5 out4 gndd v mon9 v mon 8 v mon7 v mon6 v mon5 gndd v cca v mon4 v mon3 v mon2 v mon1 gnda in4 in3 in2 v ccinp in1 mclk v ccd resetb v mon10 gndd gndd pldclk smba_out3 h v out2 h v out1 tms atdi tdi v ccj tdo tck v ccd v ccprog tdisel
lattice semiconductor isppac-powr1014/a data sheet 45 revision history date version change summary february 2006 01.0 initial release. march 2006 01.1 isppac-powr1014/a block diagram: ?eltdi changed to ?disel? pin descriptions table: ?nxp changed to ?nx? ?o n x to ?mo n x? vmo n upper range from ?.75v to ?.87v? pin descriptions table, note 4 - clari?ation for un-used vmo n pins to be tied to g n dd. absolute maximum ratings table and recommended operating conditions table: ?mo n + changed to vmo n ? digital speci?ations table: add note # 2 to isi n ktotal: ?um of maximum current sink by all digital outputs. reliable operation is not guaranteed if this value is exceeded. typographical corrections: vmon trip points and thresholds typographical corrections: ?nxp to ?nx? ?o n x to ?mo n x? may 2006 01.2 update hvout i source range: 12.5? to 100? clarify operation of adc conversions digital speci?ations table, added footnotes on i 2 c frequency tap instructions table, clarify discharge instruction of jtag. added instruction descrip- tions for others. october 2006 01.3 data sheet status changed to ?inal analog speci?ations table, reduced max. i cc to 20 ma. tightened input resistor variation to 15%. ac/transient characteristics table, tightened internal oscillator frequency variation down to 5%. digital speci?ations table, included v il and v ih speci?ations for i 2 c interface. march 2007 01.4 corrected vcci n p voltage range from "2.25v to 3.6v" to "2.25v to 5.5v". removed reference to internal pull-up resistor for signal line tdo. corrected the maximum vmon range value from 5.734v to 5.867v. removed references to vps[0:1]. august 2007 01.5 changes to hvout pin speci?ations.

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